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==Article purpose==
The purpose of this article is to:
* briefly introduce the SPI peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when necessary, how to configure the SPI peripheral and for some of them the I2S features.

==Peripheral overview==
The SPI peripheral can be used to communicate with an external devices using the SPI (Serial Peripheral Interface).<br> 
A subset of the SPI instances supports the I2S audio protocol. These '''SPI/I2S''' peripherals can alternatively be used in '''audio''' applications, when they are configured as an I2S interface. Refer to [[#Peripheral assignment|peripheral assignment chapter]] to check I2S feature support for each SPI instance.

===Features===
==== SPI main features ====
* Full-duplex, half-duplex and simplex synchronous modes.
* Slave and master modes.

==== I2S main features ====
Only available for SPI supporting I2S mode.
* Full-duplex or simplex modes.
* Slave and master modes.
* Four audio protocols supported.

==== Specific features ==== 
Some of the SPI peripheral characteristics depend on I2S support, as summarized in following table:
{| class="st-table"
! SPI modes/features
! I2S supported
! I2S not supported
|-
| Rx & TxFIFO size (N) [x 8-bit]
| 16
| 8
|-
| Maximum configurable data size [bits]
| 32
| 16
|}

Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.<br>

===Security support===
SPI6 is a '''secure''' peripheral (under ETZPC control).<br>
The other SPI instances are '''non-secure''' peripherals.

==Peripheral usage and associated software==
===Boot time===
The SPI is not used at boot time.

===Runtime===
====Overview====
The SPI6 can be allocated to: 
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be controlled in OP-TEE by the SPI OP-TEE driver

All the SPI instances can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by:
:* the SPI framework for SPI configured in SPI mode 
:* the ALSA framework for SPI configured in I2S mode
or
* the Cortex-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|STM32Cube SPI driver]]

{{InternalInfo| Add internal information here, if needed, or remove this section}}

Chapter [[#Peripheral assignment|Peripheral assignment]] describes which peripheral instance can be assigned to which context.

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Low speed interface
 | [[SPI internal peripheral|SPI]]
 | [[OP-TEE_overview|OP-TEE SPI driver]]
 | [[SPI_overview | Linux SPI framework]]
 | [[STM32CubeMP1 architecture|STM32Cube SPI driver]]
 | SPI configured in SPI mode<br>{{highlight|The OP-TEE SPI driver is not yet available}}
 |-
 | Audio
 | [[SPI internal peripheral|SPI]]
 |
 | [[ALSA_overview | Linux ALSA framework]]
 | [[STM32CubeMP1 architecture|STM32Cube SPI driver]]
 | SPI configured in I2S mode<br>{{highlight|Only for SPI supporting I2S feature}}
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be done via [[STM32CubeMX]] tool for all internal peripheral, then it can manually be completed (especially for external peripherals) according to the information given in the corresponding software framework article.

When the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 core operates in non-secure access mode, the SPI is controlled by the Linux kernel framework.

* SPI mode:
Refer to [[SPI_overview|SPI framework]] to check how to drive SPI through Linux kernel.

* I2S mode:
Refer to [[I2S Linux driver]] to drive the SPI through Linux kernel [[ALSA_overview|ALSA framework]]. Refer to [[Soundcard configuration]] to configure it through the Linux kernel device tree<ref>[[Device tree]]</ref>.

====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}
<onlyinclude>
 | rowspan="6" | Low speed interface
 | rowspan="6" | [[SPI internal peripheral|SPI]]
 | SPI2S1
 | 
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | Assignment (single choice)
 |-
 | SPI2S2
 | 
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | Assignment (single choice)
 |-
 | SPI2S3
 | 
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | Assignment (single choice)
 |-
 | SPI4
 | 
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | Assignment (single choice)
 |-
 | SPI5
 | 
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 | Assignment (single choice)
 |-
 | SPI6
 | <span title="assignable peripheral" style="font-size:21px">☐</span> 
 | <span title="assignable peripheral" style="font-size:21px">☐</span>
 |
 | Assignment (single choice)
 |-
</onlyinclude>
 |}

==References==
<references/>