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| + | == Supported Flash memory technologies == |
| | + | The STM32MP15 boards support different kind of Flash memories: |
| | + | * A SD card connected to an SDMMC interface, which is present on [[:Category:Getting started with STM32MP1 boards|Evaluation and Discovery boards]]. |
| | + | * An eMMC connected to an SDMMC interface, which is present on [[:Category:Getting started with STM32MP1 boards|Evaluation board]] only. |
| | | | |
| − | == Overview ==
| + | The next section lists all the partitions used on STM32MP15 boards (size, name and content). The following sections show how they are mapped on the different types of Flash memories. |
| − | This article shows the default memory mapping defined by STMicroelectronics in [[STM32MPU Embedded Software architecture overview|STM32MPU Embedded Software]]. It uses a subset of all memory regions that are exposed at hardware level: customers may use other memory regions or aliases that are not shown here but are described in the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]].<br />
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| | | | |
| − | == Arm core characteristics == | + | ==From Android 10.0.0 distribution== |
| − | The integration of Arm<sup>®</sup> Cortex<sup>®</sup> cores sets some constraints on the device memory mapping: the main ones are listed in this article.
| + | {{:STM32MP15 Flash mapping for Android - v1.1.0}} |
| | | | |
| − | === Reset address ===
| + | <div class="mw-collapsible mw-collapsed"> |
| − | Arm<sup>®</sup> Cortex<sup>®</sup> cores start running from address 0x00000000 on reset, which is why this address respectively points to:
| + | ==For Android 9.0.0 distribution== |
| − | * The [[STM32MP15 ROM code overview|ROM code]] on the Cortex-A7 side. This read-only memory embeds the boot code that is executed when the platform boots (and executes the [[Boot chains overview|boot chain]]) or wakes up from [[Power overview|low power STANDBY mode]].
| + | <div class="mw-collapsible-content"> |
| − | * The [[RETRAM internal memory|Retention RAM]] on the Cortex-M4 side. This needs to be loaded by the Cortex-A7 before releasing the Cortex-M4 reset (in the [[RCC internal peripheral|RCC]]) and getting it running. This is done by Linux [[Coprocessor management overview|coprocessor management]], by default.
| + | {{:STM32MP15 Flash mapping for Android - v1.0.0}} |
| − | Note: since the Cortex-A7 has its ROM code mapped at address 0x00000000, it uses a hardware alias to access the retention RAM at address 0x38000000
| + | </div></div> |
| − | | |
| − | === Cortex-M4 multiple ports ===
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| − | The Cortex-M4 is connected to the interconnect (ML-AHB) via three ports, listed below and shown in the following figure:
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| − | * I-bus is used to fetch code instructions in the 0x00000000--0x1FFFFFFF address range
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| − | * D-bus is used to read/write data in the 0x00000000--0x1FFFFFFF address range
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| − | * S-bus is used for all accesses in the 0x20000000--0xFFFFFFFF address range; all STM32MP15 internal peripherals registers are mapped in this range.<br /><br />
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| − | | |
| − | [[File:Cortex-M4 ports.png|center|link=]]<br />
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| − | | |
| − | Balancing the Cortex-M4 firmware accesses among those ports allows tuning of the system performance, which is why the [[MCU SRAM internal memory|MCU SRAM]] is defined in the first address range (from 0x10000000), but is also visible in the second range (from 0x30000000) in the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]]. <br />
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| − | <br />
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| − | Nevertheless, it is important to notice that the Cortex-M4 embedded in the STM32MP15 only allows hardware breakpoints to be set on the address range covered by the I-bus. Thus any code accessed via the S-bus has to be debugged through software breakpoints.
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| − | | |
| − | == Memory mapping ==
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| − | | |
| − | === Overall memory mapping ===
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| − | The memory mapping below is a subset of all regions that are exposed at hardware level: it shows the default configuration used in OpenSTLinux but the customer may choose a different mapping to take advantage of other address ranges defined in [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]].<br />
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| − | | |
| − | {{
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| − | ImageMap|
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| − | Image:Software memory mapping.png {{!}} frame {{!}} center{{!}} STM32MP15 memory mapping
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| − | rect 90 48 477 139 [[DDRCTRL and DDRPHYC internal peripherals | DDR]]
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| − | rect 90 158 477 187 [[STM32MP15 backup registers | Backup registers]]
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| − | rect 90 192 266 206 [[BKPSRAM internal memory | BKPSRAM]]
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| − | rect 300 245 477 260 [[FDCAN internal peripheral | CAN SRAM]]
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| − | rect 300 284 477 298 [[RETRAM internal memory | RETRAM]]
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| − | rect 512 503 688 517 [[RETRAM internal memory | RETRAM]]
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| − | rect 90 341 477 369 [[SYSRAM internal memory | SYSRAM]]
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| − | rect 300 427 477 459 [[MCU SRAM internal memory | MCU SRAM]]
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| − | rect 512 427 688 459 [[MCU SRAM internal memory | MCU SRAM]]
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| − | rect 90 494 477 517 [[STM32MP15 ROM code overview | ROM]]
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| − | }}
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| − | | |
| − | {{InternalInfo|On STM32MP15 Rev. B, the Cortex-M4 data in MCU SRAM2 should be accessed via the S-bus (from 0x30020000) instead of D-bus (from 0x10020000) since the MLAHB bus has been tuned to offer maximum performances on this path. Notice that the optimization is only affecting Data access: Instruction access is 'optimized' on either S-bus or I-bus on all SRAMs and RETRAM (even if I-bus should be preferable).}}
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| − | | |
| − | === Zoom in the Cortex-A7/Cortex-M4 shared memory ===
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| − | The figure below is a zoom of the RAM areas that are shared between the Cortex-A7 non-secure and the Cortex-M4. This mapping is STMicroelectronics' default implementation that can be freely adapted by customers to fit to other needs.<br />
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| − | | |
| − | [[File:Shared RAM memory mapping.png|center|link=]]
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| − | | |
| − | === Possible customization of shared RAM memory ===
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| − | | |
| − | As described in https://wiki.st.com/stm32mpu/wiki/MCU_SRAM_internal_memory, ST has defined a memory mapping to be able to enable all the possible use cases in parallel but this can be customized depending on customer use cases.
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| − | | |
| − | ==== Overview ====
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| − | * '''RETRAM''' is not used except for the vector table which must be stored at address 0. The rest of this memory section can be used for any purpose.
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| − | * '''MCU SRAM1''' (Code) and '''SRAM2''' (Data) sizes can be tuned depending on user needs to better use physical area of 256KB.
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| − | * '''MCU SRAM3''' (IPC Buffers) can be used for other purpose if IPC is not used
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| − | * '''MCU SRAM4''' (DMA) can be used for other purpose if DMA1 and/or DMA2 is not used in chained mode (using MDMA)
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| − | | |
| − | ==== How to do that in practice ====
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| − | | |
| − | The memory usage is defined in both Cortex contexts:
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| − | * on Cortex-A7: in Linux device tree, using [[Reserved_memory]] mechanism
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| − | * on Cortex-M4: in the linker script
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| − | To ensure the consistency of the system, both memory declarations have to be updated according to the expected configuration.
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| − | | |
| − | ===== RETRAM=====
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| − | | |
| − | By default the RETRAM is reserved for the Cortex-M4 firmware and only the vector table uses it. The base address is fixed, the vector table section of the M4 firmware needs to be at this place but other sections may be added on top.
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| − | * Linux Device tree
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| − | :"retram" memory region declaration (no update needed):
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| − | retram: retram@0x38000000 {
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| − | compatible = "shared-dma-pool";
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| − | reg = <0x38000000 0x10000>;
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| − | no-map;
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| − | };
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| − | | |
| − | :No update needed for m4_proc node.
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| − | <pre>
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| − | &m4_rproc {
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| − | memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
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| − | <&vdev0vring1>, <&vdev0buffer>;
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| − | ranges = <0x00000000 0x38000000 0x10000>,
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| − | <0x30000000 0x30000000 0x60000>,
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| − | <0x10000000 0x10000000 0x60000>;
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| − | </pre>
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| − | * Cortex-M4 STM32Cube firmware
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| − | :In STM32Cube linker script definition (.ld): keep vector table "m_interrupts" but any new section can be added on top to use RETRAM free memory space:
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| − | | |
| − | MEMORY
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| − | {
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| − | m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000298
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| − | m_any_section .... : ..................
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| − | }
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| − | | |
| − | ===== MCU SRAM4 =====
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| − | By default the MCU SRAM4 is reserved for DMA chaining for Linux features. It can be freed for some other purposes by removing following:
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| − | | |
| − | * Linux device tree
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| − | :Remove followings declarations:
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| − | <pre>
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| − | sram: sram@10050000 {
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| − | compatible = "mmio-sram";
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| − | reg = <0x10050000 0x10000>;
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| − | #address-cells = <1>;
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| − | #size-cells = <1>;
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| − | ranges = <0 0x10050000 0x10000>;
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| − | | |
| − | dma_pool: dma_pool@0 {
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| − | reg = <0x0 0x10000>;
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| − | pool;
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| − | };
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| − | };
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| − | </pre>
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| − | | |
| − | <pre>
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| − | &dma1 {
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| − | sram = <&dma_pool>;
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| − | };
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| − | | |
| − | &dma2 {
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| − | sram = <&dma_pool>;
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| − | };
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| − | </pre>
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| − | | |
| − | ===== MCU SRAM3 =====
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| − | By default the MCU SRAM3 is reserved for the IPC. It can be freed for some other purposes by removing following:
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| − | * Linux device tree
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| − | :Remove followings memory region declarations:
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| − | <pre>
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| − | vdev0vring0: vdev0vring0@10040000 {
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| − | compatible = "shared-dma-pool";
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| − | reg = <0x10040000 0x2000>;
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| − | no-map;
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| − | };
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| − | | |
| − | vdev0vring1: vdev0vring1@10042000 {
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| − | compatible = "shared-dma-pool";
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| − | reg = <0x10042000 0x2000>;
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| − | no-map;
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| − | };
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| − | | |
| − | vdev0buffer: vdev0buffer@10044000 {
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| − | compatible = "shared-dma-pool";
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| − | reg = <0x10044000 0x4000>;
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| − | no-map;
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| − | };
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| − | </pre>
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| − | :Remove associated reference in m4_rproc node: | |
| − | | |
| − | &m4_rproc {
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| − | memory-region = <&retram>, <&mcuram>, <&mcuram2>,
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| − | {{Highlight|<&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer}};
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| − | ranges = <0x00000000 0x38000000 0x10000>,
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| − | <0x30000000 0x30000000 0x60000>,
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| − | <0x10000000 0x10000000 0x60000>;
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| − | * Cortex-M4 STM32Cube firmware:
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| − | :Must be aligned with STM32Cube linker script definition (.ld), remove "m_ipc_shm":
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| − | MEMORY
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| − | {
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| − | m_ipc_shm (RW) : ORIGIN = 0x10040000, LENGTH = 0x00008000
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| − | }
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| − | | |
| − | ===== MCU SRAM1 & SRAM2 =====
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| − | By default the MCU SRAM1 & SRAM2 are reserved for the STM32Cube firmware. This can be optimized depending on the firmware needs.
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| − | | |
| − | * Linux device tree
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| − | :Only one section is declared for STM32Cube firmware code and data in Linux device tree
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| − | :Notice that the MCURAM is aliased so accessible at addresses 0x10000000 or 0x30000000. In consequence mcuram and mcuram2 memory sections definitions have to be coherent.
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| − | | |
| − | mcuram: mcuram@ {{Highlight|0x30000000}} {
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| − | compatible = "shared-dma-pool";
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| − | reg = {{Highlight|<0x30000000 0x40000>}}; /* define memory base and size for Cortex-M4 firmware*/
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| − | no-map;
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| − | };
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| − | mcuram2: mcuram2@{{Highlight|0x10000000}} {
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| − | compatible = "shared-dma-pool";
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| − | reg = {{Highlight|<0x10000000 0x40000>}}; /* define memory base and size for Cortex-M4 firmware*/
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| − | no-map;
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| − | };
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| − |
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| − | :No update needed for m4_proc node.
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| − | <pre>
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| − | &m4_rproc {
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| − | memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
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| − | <&vdev0vring1>, <&vdev0buffer>;
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| − | | |
| − | ranges = <0x00000000 0x38000000 0x10000>,
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| − | <0x30000000 0x30000000 0x60000>,
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| − | <0x10000000 0x10000000 0x60000>;
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| − | </pre> | |
| − | | |
| − | * Cortex-M4 STM32Cube firmware
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| − | :The memory mapping you have defined on Linux side (freed for M4 usage) needs to be consistent with STM32Cube linker script definition (.ld):
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| − | | |
| − | MEMORY
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| − | {
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| − | m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000298
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| − | m_text (RX) : ORIGIN = 0x10000000, LENGTH = 0x00020000
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| − | m_data (RW) : ORIGIN = 0x10020000, LENGTH = 0x00020000
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| − | m_ipc_shm (RW) : ORIGIN = 0x10040000, LENGTH = 0x00008000
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| − | }
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| | | | |
| | <noinclude> | | <noinclude> |
| | [[Category:STM32MP15 platform configuration|2]] | | [[Category:STM32MP15 platform configuration|2]] |
| − | {{PublicationRequestId | 15403 | 20120-03-20 | AnneJ}} | + | [[Category:Android]] |
| | + | [[Category:Flash mapping for Android]] |
| | + | {{PublicationRequestId | 13246 | 2019-09-12 | AnneJ}} |
| | </noinclude> | | </noinclude> |
