“QUADSPI device tree configuration”的版本间的差异
| 第9行： | 第9行： | ||
== DT bindings documentation == | == DT bindings documentation == | ||
| − | + | QUADSPI设备树绑定由以下组成： | |
* generic SPI-NOR / SPI-NAND Flash memory bindings <ref name="spi_busses_bindings">{{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-bus.txt}}</ref>. | * generic SPI-NOR / SPI-NAND Flash memory bindings <ref name="spi_busses_bindings">{{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-bus.txt}}</ref>. | ||
| 第15行： | 第15行： | ||
* QUADSPI driver bindings <ref> {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt}} </ref>. | * QUADSPI driver bindings <ref> {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt}} </ref>. | ||
| − | + | 在接下来的章节中，SPI-NAND绑定只与{{EcosystemRelease | revision=1.1.0 | range=and after}}兼容。 | |
== DT configuration == | == DT configuration == | ||
2020年11月10日 (二) 11:45的版本
目录
Article purpose
本文介绍如何在将 QUADSPI internal peripheral 分配给 Linux®操作系统时对其进行配置。 在这种情况下，它由MTD framework控制.
使用device tree 机制执行配置，该机制提供由STM32 QUADSPI Linux驱动程序和MTD框架使用的QUADSPI外围设备的硬件描述。
如果外围设备已分配给另一个执行上下文，请参阅[[[How to assign an internal peripheral to a runtime context]] 文章，了解有关外围设备分配和配置的指南。
DT bindings documentation
QUADSPI设备树绑定由以下组成：
- generic SPI-NOR / SPI-NAND Flash memory bindings [1].
- QUADSPI driver bindings [2].
在接下来的章节中，SPI-NAND绑定只与ecosystem release ≥ v1.1.0{{#set:Ecosystem release=revision of a previous flow 1.1.0}} 兼容。
DT configuration
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.
STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.
DT configuration (STM32 level)
The QUADSPI peripheral node is located in stm32mp157c.dtsi[3] file.
qspi: spi@58003000 { Comments
compatible = "st,stm32f469-qspi";
reg = <0x58003000 0x1000>, --> Register location
<0x70000000 0x10000000>; --> Memory mapping address
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; --> The interrupt number used
dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>, --> DMA specifiers [4]
<&mdma1 22 0x10 0x100008 0x0 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
status = "disabled";
};
 |
This device tree part related to the STM32 should be kept as is, the customer should not modify it. |
DT configuration (board level)
The QUADSPI peripheral may connect a maximum of 2 SPI-NOR Flash memories.
SPI-NOR Flash memory nodes [1] must be children of the QUADSPI peripheral node.
&qspi { Comments
pinctrl-names = "default", "sleep"; --> For pinctrl configuration, please refer to Pinctrl device tree configuration
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
reg = <0x58003000 0x1000>,
<0x70000000 0x4000000>; --> Overwrite the memory map to the Flash device size, avoid the waste of virtual memory that will not be used
#address-cells = <1>;
#size-cells = <0>;
status = "okay"; --> Enable the node
flash0: mx66l51235l@0 {
compatible = "jdec,spi-nor";
reg = <0>; --> Chip select number
spi-rx-bus-width = <4>; --> The bus width (number of data wires used)
spi-max-frequency = <108000000>; --> Maximum SPI clocking speed of device in Hz
#address-cells = <1>;
#size-cells = <1>;
};
};
DT configuration example
The below example shows how to configure the QUADSPI peripheral when 1 SPI-NAND Flash and 1 SPI-NOR Flash memories are connected.
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
reg = <0x58003000 0x1000>,
<0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
compatible = "jdec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
flash1: mt29f2g01abagd@1 {
compatible = "spi-nand";
reg = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <133000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
How to configure the DT using STM32CubeMX
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.
References
Please refer to the following links for full description:
- ↑ 1.01.1 Documentation/devicetree/bindings/spi/spi-bus.txt| |}} Documentation/devicetree/bindings/spi/spi-bus.txt
- ↑ Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt| |}} Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt
- ↑ arch/arm/boot/dts/stm32mp157c.dtsi| |}} arch/arm/boot/dts/stm32mp157c.dtsi
- ↑ Documentation/devicetree/bindings/dma/stm32-mdma.txt| |}} Documentation/devicetree/bindings/dma/stm32-mdma.txt
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